Nexabit patents, in reverse order of filing date:


6,272,567  System for interposing a multi-port internally cached DRAM in a control path for temporarily storing multicast start of packet data until such can be passed .  S Pal, Rajib Ray, Opalka Aug 7, 2001 (filed Nov 24, 1998)


5,991,163  Electronic circuit board assembly and method of closely stacking boards and cooling the same .  Marconi, T Bilodeau, Rigby. Nov 29, 1999 (filed Nov 12, 1998)


6,237,130  Chip layout for implementing arbitrated high speed switching access of pluralities of I/O data ports to internally cached DRAM banks and the like .  Soman, Opalka, Chatter. May 22, 2001 (filed Oct 29, 1998)


6,275,508  Method of and system for processing datagram headers for high speed computer network interfaces at low clock speeds, utilizing scalable algorithms for performing such network header adaptation (SAPNA) .  Benz, Aggarwal, Aug 14, 2001 (filed April 21, 1998).


6,249,525  Method of and apparatus for inserting and/or deleting escape characters into and from data packets and datagrams therefor on high speed data stream networking lines . Aggarwal, Miller.  June 19, 2001 (filed March 27, 1998)


6,138,219  Method of and operating architectural enhancement for multi-port internally cached dynamic random access memory (AMPIC DRAM) systems, eliminating external control paths and random memory addressing, while providing zero bus contention for DRAM access .  Soman, S Pal. Oct 24, 2000 (filed Mar 27, 1998)


6,085,290  Method of and apparatus for validating data read out of a multi port internally cached dynamic random access memory (AMPIC DRAM)   Smith, Conlin. July 4, 2000 (filed Mar 10, 1998)


6,259,699  System architecture for and method of processing packets and/or cells in a common switch .  Opalka, Aggarwal, Kong, Firth, Costantino. July 10, 2001 (filed Dec 30, 1997)


6,212,597  Apparatus for and method of architecturally enhancing the performance of a multi-port internally cached (AMPIC) DRAM array and like .  Conlin, Wright, Marconi, Chatter. April 3, 2001 (filed July 28, 1997)


5,918, 074 System architecture for and method of dual path data processing and management of packets and/or cells and the like .  Wright, Marconi, Conlin, Opalka. June 29, 1999 (filed July 25, 1997



6,069,879 Method of and system architecture for high speed dual symmetric full duplex operation of asymmetric digital subscriber lines  Chatter, May 30, 2000 (filed Nov 14, 1996)

5,799,209 Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration  Chatter, Aug 25, 1998 (filed Dec 29, 1995)



Chatter: 2+2

Opalka: 4

Marconi: 3

Conlin: 3

Aggarwal: 3

Soman: 2

Wright: 2

Pal: 2

Smith: 1

Kong: 1

Benz: 1

Miller: 1

Firth,: 1

Costantino: 1

Bilodeau: 1

Rigby: 1

Ray: 1